The ongoing reduction in size of electronic device elements poses problems in device performance which must be addressed using new materials and fabrication techniques. These problems are especially acute in the case of gate structures for high-performance CMOS devices. A typical CMOS gate structure is shown schematically in FIG. 1. Gate structure 100 (often called a gate stack) is fabricated on the surface of substrate 1, which typically is a semiconductor wafer (e.g. Si, Ge, SiGe, as well as semiconductors over a buried insulator). Source and drain regions 22, 23 are formed near the surface of the wafer. Gate structure 100 includes conducting element 110 (typically polysilicon; p+ doped and n+ doped in PFETs and NFETs respectively) overlying dielectric layer 111. In present-day devices the equivalent oxide thickness of the gate dielectric has been reduced to less than 2 nm. At the same time, linewidths have been reduced so that the lateral extent of gate structure 100 is now in the sub-65 nm range.
With present-day gate dielectric thicknesses, it is desirable to minimize the polysilicon depletion effect, which occurs when the gate is turned on and a region devoid of charge forms at the polysilicon/dielectric interface (interface 112a in FIG. 1). The appearance of this depletion region reduces the capacitance of the gate and thus increases the electrical thickness, so that device performance is reduced. If the polysilicon depletion region could be eliminated, the electrical dielectric thickness would be reduced with no substantial increase in the leakage current. This would permit improved device performance without a further reduction in the thickness of the gate dielectric 112.
It therefore is desirable to eliminate the polysilicon from the gate structure (or at least remove the polysilicon from contact with the gate dielectric), as several benefits may be obtained. The elimination of the polysilicon depletion effect would decrease the effective electrical thickness of the gate dielectric. Interactions between the polysilicon and gate dielectric materials would be avoided, which in turn would avoid the problem of boron penetration. This would lead to faster devices which consume less power. Replacing the polysilicon with other materials also may enable new designs for gate stacks which are compatible with high-k gate dielectrics.
Recently there has been substantial interest in replacing polysilicon gate conductors with metal silicide gate electrodes. In general, forming a silicided gate involves reacting a layer of metal with an underlying layer of silicon (polysilicon or amorphous silicon), which in turn is in contact with the gate dielectric. A substantial number of additional process steps are required as compared to fabrication of a conventional polysilicon gate. Furthermore, a typical silicide gate fabrication scheme requires chemical-mechanical polishing (CMP) or etching back of the polysilicon layer. These processes often fail to provide adequate uniformity (across the wafer) in the polysilicon thickness. This in turn results in low-quality silicided gates and low device yields.
Accordingly, there is a need for a metal silicide gate fabrication process which minimizes the number of additional steps, and avoids the uniformity problems associated with conventional fabrication techniques.